Estimation of Power Dissipation of CMOS and finFET based 6T SRAM Memory
نویسنده
چکیده
This paper provides the estimation of power dissipation of CMOS and finFET based 6T SRAM Memory. CMOS expertise feature size and threshold voltage have been scaling down for decades for achieving high density and high performance. The continuing reduce in the feature size and the corresponding increases in chip density and operating frequency have made power consumption a major concern in VLSI design. Extreme power dissipation in integrated circuits discourages their use in moveable systems. Low threshold voltage also results in enlarged sub-threshold leakage current because transistors cannot be turned off completely. For these reasons, leakage power dissipation, has become a major part of total power consumption for current and future silicon technologies. FinFET evolving to be a promising technology in this regard .In this the designing, modeling and optimizing the 6-T SRAM cell device is done.
منابع مشابه
Impact of Fin Dimensions and Gate DielectricThickness on the Static Power Dissipation of 6T- FinFET SRAM Cell
The Triple gate FinFET architecture has emerged as a viable contender for the ultimate scalability of CMOS devices. FinFET structure offers better control over device leakage currents than the conventional bulk MOSFET structure. In this paper, we present the 6 transistor (6T) SRAM cell implementation using the 22 nm gate length FinFET devices modeled using a 3-D device simulator. The performanc...
متن کاملComparison of Conventional 6T SRAM cell and FinFET based 6T SRAM Cell Parameters at 45nm Technology
When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MO...
متن کاملAutonomous Gate Twin Fin 6T SRAM Cell Victimization Outpouring Reduction Techniques
Scaling of gadgets in mass CMOS engineering helps short direct impacts and increment in spillage. Static arbitrary access memory (SRAM) is required to involve 90% of the zone of Soc. Since spillage turns into the essential variable in SRAM cell, it is actualized utilizing FinFet. FinFet gadgets got to be better option for profound submicron advances. In this paper, 6t SRAM cell is actualized ut...
متن کاملIndependent Gate Finfet Sram Cell Using Leakage Reduction Techniques
1 Research Scholar of Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India 2 Professor, Dept. of Electronics and Communication, Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India. __________________________________________________________________________________________ Abstract: Scaling of devices in bulk CMOS technology contributes to short channel effe...
متن کاملAverage and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm, and 45nm CMOS Technology for a High Speed SRAMs
A lot of consideration has been given to problems arising due to power dissipation. Different ideas have been proposed by many researchers from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between the power, delay and area. This is why; the designers are required to choose appropriate techniques that satisfy application and product...
متن کامل